1. Field of the Invention
The present invention relates to a method and an apparatus for preventing a glitch, more particularly to, a method and an apparatus for preventing a glitch caused by a clock switching in a phase-interpolating circuit.
2. Description of the Prior Arts
A phase-interpolating circuit, which acts as a phase generating circuit, has a function for mixing two designated input clocks according to a desirable ratio, so as to generate a clock having a phase located between the two inputted clocks. Since the phase interpolating circuit is capable of generating a clock with designated phase, hence, the aforesaid circuit, is widely applicable such as clock multiplying unit circuit, clock generating circuit and clock/data recovery.
FIG. 1 illustrates a popular phase-interpolating circuit 10, where VO1P, VO1N, and VO0P, VO0N are deemed respectively as a pair of differential clock signal inputs with contiguous phases. The skilled artisan can varies a ratio between the variable current sources 101 and 102, namely α, so as to determined the designated ratio in an outputted clock for these two input clocks. In real application, the phase-interpolating circuit 10 usually co-operates with a phase rotator circuit, where the phase rotator generates desirable information for an output clock phase, and the circuit 10 bases upon the outputs of the phase rotator circuit to generate a desirable clock phase.
As FIG. 2 illustrates, the phase rotator bases upon the desirable output clock phase and chooses two contiguous clocks, which act as the inputs for the circuit 10, and meanwhile, determines the α value. A interpolation is applied to the two input clocks according to the α value so as to acquire a desirable output phase.
The design criterion for the phase rotator/phase-interpolating system, is to ensure the output phase is devoid of glitch while output clocks switch their phases. As FIG. 3 illustrates, while the designated output phase jumps from a contiguous clock set such as clock 1 and clock 2 to another contiguous clock set such as clock 2 and clock 3, inevitably, there exists a demand for a switching for the input clocks of the phase-interpolating circuit. Correspondingly, the input clock for the phase-interpolating circuit needs to switch from a weighted phase between clock 1 and clock 2 to another weighted phase between clock 2 and clock 3, namely, the VO1P, VO1N of circuit 10 have an input clock switching from clock 1 to clock 3. And during the clock switching, however, if the switching timing is improper, exemplarily, while enable 1 or enable 3 located at a rising or falling edge, if the clock 1 or clock 3 are of logic high, then there will be a glitch at the VO1P or VO1N side so as to introduce a glitch at the output side of the circuit 10. For preventing the foregoing drawback, the conventional approach is, during the clock switching, to ensure the clock 1 and clock 3 both locate at logic low, consequently, at the time of input clock switching, phase is devoid of glitch at switching spot so as to prevent the glitch. However, for ensuring the logic low, inevitably, an extraordinary sequential control circuit is needed, and the corresponding and possible delay situations must be considered, so as to increase the circuit design complexities and difficulties. For addressing the foregoing issues, the present invention discloses a new glitch prevention mechanism, for effectively prevent the foregoing complicated sequential control circuit, and reduce the circuit design difficulties and correspondingly saving area and power consuming.
Accordingly, in view of the above drawbacks, it is an imperative that a method and an apparatus for preventing glitches so as to greatly improve the influence of clock switching vs. output phase.